Direct Form Structure

FIR Filter Architecture

Visualize the signal flow through the fundamental building blocks of a digital filter: delays, multipliers, and adders.

Direct Form FIR Filter (Order M = 3)

Animate Signal Flow
x[n] z⁻¹ z⁻¹ h[0] h[1] h[2] + + y[n]
y[n] = h[0]·x[n] + h[1]·x[n−1] + h[2]·x[n−2] + ... + h[M]·x[n−M]

Filter Components

z⁻¹

Delay Element (z⁻¹)

Called a Unit Delay or shift register. It delays the digital signal by exactly one sample period. A sequence of delays stores the past values of the input signal x[n-1], x[n-2], etc., forming the memory of the filter.

Multiplier & Coefficient (h)

Each multiplier scales the delayed signal by a fixed constant value h[k], which is the filter coefficient (or impulse response tap). The number of multipliers determines the order M of the filter.

Adder

The adders sum together all the scaled delayed signals. The final output y[n] is the accumulation of these products, which is the mathematical definition of discrete convolution.